125 lines
2.8 KiB
C
125 lines
2.8 KiB
C
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/*
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <util.h>
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#include <asm/cpuid.h>
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#include <asm/cpu_caps.h>
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#include <asm/io.h>
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#include <asm/tsc.h>
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#define CAL_MS 10U
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static uint32_t tsc_khz;
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static uint64_t pit_calibrate_tsc(uint32_t cal_ms_arg)
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{
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#define PIT_TICK_RATE 1193182U
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#define PIT_TARGET 0x3FFFU
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#define PIT_MAX_COUNT 0xFFFFU
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uint32_t cal_ms = cal_ms_arg;
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uint32_t initial_pit;
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uint16_t current_pit;
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uint32_t max_cal_ms;
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uint64_t current_tsc;
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uint8_t initial_pit_high, initial_pit_low;
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max_cal_ms = ((PIT_MAX_COUNT - PIT_TARGET) * 1000U) / PIT_TICK_RATE;
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cal_ms = min(cal_ms, max_cal_ms);
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/* Assume the 8254 delivers 18.2 ticks per second when 16 bits fully
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* wrap. This is about 1.193MHz or a clock period of 0.8384uSec
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*/
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initial_pit = (cal_ms * PIT_TICK_RATE) / 1000U;
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initial_pit += PIT_TARGET;
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initial_pit_high = (uint8_t)(initial_pit >> 8U);
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initial_pit_low = (uint8_t)initial_pit;
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/* Port 0x43 ==> Control word write; Data 0x30 ==> Select Counter 0,
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* Read/Write least significant byte first, mode 0, 16 bits.
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*/
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pio_write8(0x30U, 0x43U);
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pio_write8(initial_pit_low, 0x40U); /* Write LSB */
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pio_write8(initial_pit_high, 0x40U); /* Write MSB */
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current_tsc = rdtsc();
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do {
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/* Port 0x43 ==> Control word write; 0x00 ==> Select
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* Counter 0, Counter Latch Command, Mode 0; 16 bits
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*/
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pio_write8(0x00U, 0x43U);
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current_pit = (uint16_t)pio_read8(0x40U); /* Read LSB */
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current_pit |= (uint16_t)pio_read8(0x40U) << 8U; /* Read MSB */
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/* Let the counter count down to PIT_TARGET */
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} while (current_pit > PIT_TARGET);
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current_tsc = rdtsc() - current_tsc;
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return (current_tsc / cal_ms) * 1000U;
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}
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/*
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* Determine TSC frequency via CPUID 0x15 and 0x16.
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*/
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static uint64_t native_calibrate_tsc(void)
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{
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uint64_t tsc_hz = 0UL;
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const struct cpuinfo_x86 *cpu_info = get_pcpu_info();
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if (cpu_info->cpuid_level >= 0x15U) {
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uint32_t eax_denominator, ebx_numerator, ecx_hz, reserved;
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cpuid_subleaf(0x15U, 0x0U, &eax_denominator, &ebx_numerator,
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&ecx_hz, &reserved);
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if ((eax_denominator != 0U) && (ebx_numerator != 0U)) {
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tsc_hz = ((uint64_t) ecx_hz *
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ebx_numerator) / eax_denominator;
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}
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}
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if ((tsc_hz == 0UL) && (cpu_info->cpuid_level >= 0x16U)) {
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uint32_t eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
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cpuid_subleaf(0x16U, 0x0U, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
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tsc_hz = (uint64_t) eax_base_mhz * 1000000U;
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}
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return tsc_hz;
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}
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void calibrate_tsc(void)
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{
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uint64_t tsc_hz;
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tsc_hz = native_calibrate_tsc();
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if (tsc_hz == 0U) {
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tsc_hz = pit_calibrate_tsc(CAL_MS);
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}
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tsc_khz = (uint32_t)(tsc_hz / 1000UL);
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}
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uint32_t get_tsc_khz(void)
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{
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return tsc_khz;
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}
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/* external API */
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uint64_t cpu_ticks(void)
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{
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return rdtsc();
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}
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uint32_t cpu_tickrate(void)
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{
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return tsc_khz;
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}
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