39 lines
1.5 KiB
ReStructuredText
39 lines
1.5 KiB
ReStructuredText
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.. _multi-arch-support:
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Hypervisor Multi-Architecture and RISC-V Support
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################################################
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.. note:: This is a preliminary draft of a planned and as yet unreleased effort
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to port the ACRN Hypervisor to non-Intel architectures.
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From its first release in July 2018, the ACRN Hypervisor was designed for and
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targeted to Intel platforms and relied on Intel Virtualization Technology (Intel
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VT). From that base, we're expanding support to enable the ACRN hypervisor to
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RISC-V64 architecture with a Hypervisor Extension.
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RISC-V Support
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**************
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Adding multi-architecture support begins by refining the current architecture
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abstraction layer and defining architecture-neutral APIs covering the management
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of cores, caches, memory, interrupts, timers, and hardware virtualization
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facilities. Then an implementation of those APIs for RISC-V will be introduced.
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Based on its wide availability and flexibility, QEMU is the first RISC-V
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(virtual) platform this project targets. Real platforms may be selected later
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based on business and community interests.
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Current State
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=============
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This project is currently under development and is not yet ready for production.
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Once this support is implemented and has sufficient quality, this port will
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become a part of the upstream ACRN project and we'll continue development there
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and encourage contributions by the ACRN community.
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License
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=======
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This project will be released under the BSD-3-Clause license, the same as the
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rest of project ACRN.
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