2019-01-28 19:48:22 +08:00
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/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CAT_H
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#define CAT_H
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/* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */
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struct cat_hw_info {
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bool support; /* If L2/L3 CAT supported */
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bool enabled; /* If any VM setup CLOS */
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uint32_t bitmask; /* Used by other entities */
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uint16_t cbm_len; /* Length of Cache mask in bits */
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uint16_t clos_max; /* Maximum CLOS supported, the number of cache masks */
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uint32_t res_id;
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};
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extern struct cat_hw_info cat_cap_info;
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2019-01-30 19:08:19 +08:00
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void setup_clos(uint16_t pcpu_id);
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2019-01-28 19:48:22 +08:00
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#define CAT_RESID_L3 1U
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#define CAT_RESID_L2 2U
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int32_t init_cat_cap_info(void);
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#endif /* CAT_H */
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