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acrn-hypervisor/hypervisor/arch/x86/cpu_primary.S

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initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
license: Replace license text with SPDX tag Replace the BSD-3-Clause boiler plate license text with an SPDX tag. Fixes: #189 Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-26 01:49:13 +08:00
* SPDX-License-Identifier: BSD-3-Clause
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
*/
#include <cpu.h>
#include <mmu.h>
#include <gdt.h>
#include <idt.h>
#include <msr.h>
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* NOTE:
*
* MISRA C requires that all unsigned constants should have the suffix 'U'
* (e.g. 0xffU), but the assembler may not accept such C-style constants. For
* example, binutils 2.26 fails to compile assembly in that case. To work this
* around, all unsigned constants must be explicitly spells out in assembly
* with a comment tracking the original expression from which the magic
* number is calculated. As an example:
*
* /* 0x00000668 =
* * (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) *\/
* movl $0x00000668, %eax
*
* Make sure that these numbers are updated accordingly if the definition of
* the macros involved are changed.
*/
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* MULTIBOOT HEADER */
#define MULTIBOOT_HEADER_MAGIC 0x1badb002
#define MULTIBOOT_HEADER_FLAGS 0x00000002 /*flags bit 1 : enable mem_*, mmap_**/
hv: init: save boot context from bootloader/bios Add code to save boot context, which is prepare by the bootloader or BIOS, the context can be used to init sos vmcs, such as GDT, IDT, segment selectors, control registers, ia32_efer. In this way, HV can leverage the data structures built by bootloader or BIOS, without creating them in HV. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-07-28 13:50:58 +08:00
.extern cpu_primary_save32
.extern cpu_primary_save64
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
.section multiboot_header, "a"
.align 4
/* header magic */
.long MULTIBOOT_HEADER_MAGIC
/* header flags - flags bit 6 : enable mmap_* */
.long MULTIBOOT_HEADER_FLAGS
/* header checksum = -(magic + flags) */
.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
.section entry, "ax"
.align 8
.code32
.global cpu_primary_start_32
cpu_primary_start_32:
hv: init: save boot context from bootloader/bios Add code to save boot context, which is prepare by the bootloader or BIOS, the context can be used to init sos vmcs, such as GDT, IDT, segment selectors, control registers, ia32_efer. In this way, HV can leverage the data structures built by bootloader or BIOS, without creating them in HV. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-07-28 13:50:58 +08:00
/* save the MULTBOOT magic number & MBI */
movl %eax, (boot_regs)
movl %ebx, (boot_regs+4)
/* Save boot context from 32bit mode */
call cpu_primary_save_32
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* Disable interrupts */
cli
/* Clear direction flag */
cld
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* detect whether it is in long mode
*
* 0xc0000080 = MSR_IA32_EFER
*/
movl $0xc0000080, %ecx
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
rdmsr
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* 0x400 = MSR_IA32_EFER_LMA_BIT */
test $0x400, %eax
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* jump to 64bit entry if it is already in long mode */
jne cpu_primary_start_64
/* Disable paging */
mov %cr0, %ebx
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* 0x7fffffff = ~CR0_PG */
andl $0x7fffffff, %ebx
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
mov %ebx, %cr0
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* Set DE, PAE, MCE and OS support bits in CR4
* 0x00000668 =
* (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) */
movl $0x00000668, %eax
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
mov %eax, %cr4
/* Set CR3 to PML4 table address */
movl $cpu_boot32_page_tables_start, %edi
mov %edi, %cr3
/* Set LME bit in EFER */
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* 0xc0000080 = MSR_IA32_EFER */
movl $0xc0000080, %ecx
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
rdmsr
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* 0x00000100 = MSR_IA32_EFER_LME_BIT */
orl $0x00000100, %eax
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
wrmsr
/* Enable paging, protection, numeric error and co-processor
monitoring in CR0 to enter long mode */
mov %cr0, %ebx
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
/* 0x80000023 = (CR0_PG | CR0_PE | CR0_MP | CR0_NE) */
orl $0x80000023, %ebx
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
mov %ebx, %cr0
/* Load temportary GDT pointer value */
mov $cpu_primary32_gdt_ptr, %ebx
lgdt (%ebx)
/* Perform a long jump based to start executing in 64-bit mode */
HV:treewide:Replace HOST_GDT_RING0_CODE/DATA_SEL with constant MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, HOST_GDT_RING0_CODE_SEL and HOST_GDT_RING0_DATA_SEL must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. V1-->V2: Update commit information about HOST_GDT_RING0_CODE_SEL and HOST_GDT_RING0_DATA_SEL. V2-->V3: Update comment for HOST_GDT_RING0_CODE_SEL in assembly code. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-13 16:27:30 +08:00
/* 0x0008 = HOST_GDT_RING0_CODE_SEL */
ljmp $0x0008, $primary_start_long_mode
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
.code64
.org 0x200
.global cpu_primary_start_64
cpu_primary_start_64:
/* save the MULTBOOT magic number & MBI */
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
lea boot_regs(%rip), %rax
movl %edi, (%rax)
movl %esi, 4(%rax)
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
hv: init: save boot context from bootloader/bios Add code to save boot context, which is prepare by the bootloader or BIOS, the context can be used to init sos vmcs, such as GDT, IDT, segment selectors, control registers, ia32_efer. In this way, HV can leverage the data structures built by bootloader or BIOS, without creating them in HV. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-07-28 13:50:58 +08:00
/* Save boot context from 64bit mode */
call cpu_primary_save_64
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
primary_start_long_mode:
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
/* Initialize temporary stack pointer */
lea _ld_bss_end(%rip), %rsp
HV:treewide:Add 16-bit atomic operations and update vpid type There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 11:09:10 +08:00
/*0x1000 = CPU_PAGE_SIZE*/
add $0x1000,%rsp
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
/* 16 = CPU_STACK_ALIGN */
and $(~(16 - 1)),%rsp
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
/*
* Fix up the .rela sections
* Notes: this includes the fixup to IDT tables and temporary
* page tables
*/
hv: build hypervisor as PIE (position-independent executable) Build and link hypervisor with "-pie" and remove static linking so that it generates .rela sections for relocation Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin fengwei <fengwei.yin@intel.com>
2018-06-23 01:25:24 +08:00
call _relocate
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* Load temportary GDT pointer value */
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
lea cpu_primary32_gdt_ptr(%rip), %rbx
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
lgdt (%ebx)
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
/* Set the correct long jump address */
lea jmpbuf(%rip), %rax
lea after(%rip), %rbx
mov %rbx, (%rax)
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
rex.w ljmp *(%rax)
.data
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
jmpbuf: .quad 0
HV:treewide:Replace HOST_GDT_RING0_CODE/DATA_SEL with constant MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, HOST_GDT_RING0_CODE_SEL and HOST_GDT_RING0_DATA_SEL must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. V1-->V2: Update commit information about HOST_GDT_RING0_CODE_SEL and HOST_GDT_RING0_DATA_SEL. V2-->V3: Update comment for HOST_GDT_RING0_CODE_SEL in assembly code. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-13 16:27:30 +08:00
/* 0x0008 = HOST_GDT_RING0_CODE_SEL */
.word 0x0008
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
.text
after:
// load all selector registers with appropriate values
xor %edx, %edx
lldt %dx
HV:treewide:Replace HOST_GDT_RING0_CODE/DATA_SEL with constant MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, HOST_GDT_RING0_CODE_SEL and HOST_GDT_RING0_DATA_SEL must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. V1-->V2: Update commit information about HOST_GDT_RING0_CODE_SEL and HOST_GDT_RING0_DATA_SEL. V2-->V3: Update comment for HOST_GDT_RING0_CODE_SEL in assembly code. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-13 16:27:30 +08:00
/* 0x10 = HOST_GDT_RING0_DATA_SEL*/
movl $0x10,%eax
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
mov %eax,%ss // Was 32bit POC Stack
mov %eax,%ds // Was 32bit POC Data
mov %eax,%es // Was 32bit POC Data
mov %edx,%fs // Was 32bit POC Data
mov %edx,%gs // Was 32bit POC CLS
hv: fixup addresses in the assembly code for relocation In cpu_primary.S - Assign %rsp in cpu_primary_start_64(), so we can call _relocate() before any references to the symbols that need to be patched - Move lidtq instruction and the IDT fixup code after _relocate() call - In code64 part, replace 'mov' with 'lea' for correct addressing - No relocation is needed in code32 part In trampoline.S: - add trampoline_spinlock_ptr pointer, so we may be able to fixup trampoline code in HV Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-06-23 01:02:22 +08:00
/*
* Fix up the IDT desciptors
* The relocation delta in IDT tables has been fixed in _relocate()
*/
leal HOST_IDT(%rip), %edx
movl $HOST_IDT_ENTRIES, %ecx
.fixup_idt_entries:
xorl %eax, %eax
xchgl %eax, 12(%edx) /* Set rsvd bits to 0; eax now has
high 32 of entry point */
xchgl %eax, 8(%edx) /* Set bits 63..32 of entry point;
eax now has low 32 of entry point */
movw %ax, (%edx) /* Set bits 0-15 of procedure entry
point */
shr $16, %eax
movw %ax, 6(%edx) /* Set bits 16-31 of entry point */
addl $X64_IDT_DESC_SIZE,%edx
loop .fixup_idt_entries
/* Load IDT */
lea HOST_IDTR(%rip), %rbx
lidtq (%rbx)
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* continue with chipset level initialization */
call bsp_boot_init
loop:
jmp loop
.align 4
.global boot_regs
boot_regs:
.long 0x00000000
.long 0x00000000
/* GDT table */
.align 4
cpu_primary32_gdt:
.quad 0x0000000000000000
.quad 0x00af9b000000ffff
.quad 0x00cf93000000ffff
cpu_primary32_gdt_end:
/* GDT pointer */
.align 2
cpu_primary32_gdt_ptr:
.short (cpu_primary32_gdt_end - cpu_primary32_gdt) - 1
.quad cpu_primary32_gdt
/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
HV:treewide:Add 16-bit atomic operations and update vpid type There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 11:09:10 +08:00
/*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
.global cpu_boot32_page_tables_start
cpu_boot32_page_tables_start:
hv: mmu: cleanup mmu.h Remove unused Macro defininion. Tracked-On: #1124 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 16:11:17 +08:00
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
.quad cpu_primary32_pdpt_addr + 0x3
HV:treewide:Add 16-bit atomic operations and update vpid type There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 11:09:10 +08:00
/*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
cpu_primary32_pdpt_addr:
address = 0
.rept 4
hv: mmu: cleanup mmu.h Remove unused Macro defininion. Tracked-On: #1124 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 16:11:17 +08:00
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
.quad cpu_primary32_pdt_addr + address + 0x3
HV:treewide:Add 16-bit atomic operations and update vpid type There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 11:09:10 +08:00
/*0x1000 = CPU_PAGE_SIZE*/
address = address + 0x1000
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
.endr
HV:treewide:Add 16-bit atomic operations and update vpid type There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 11:09:10 +08:00
/*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
cpu_primary32_pdt_addr:
address = 0
.rept 2048
hv: mmu: cleanup mmu.h Remove unused Macro defininion. Tracked-On: #1124 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 16:11:17 +08:00
/* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
HV: treewide: fix C-style unsigned constants in assembly MISRA C requires that unsigned constants should have the 'U' suffix, while this C syntax is not accepted by binutils assembler per binutil manual. This patch explicitly spells out the unsigned constants used in the assembly files while tracking the original expressions in comments. This fixes build failure when using binutils <= 2.26. v2 -> v3: * Explicitly spell out the unsigned constants in assembly, instead of duplicating the macros in headers which break the integrity of the definitions. v1 -> v2: * Define different macros instead of wrapping all unsigned constants. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 22:50:58 +08:00
.quad address + 0x83
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
address = address + 0x200000
.endr