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acrn-hypervisor/hypervisor/arch/x86/wakeup.S

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hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
/*
Update copyright year range in code headers Modified the copyright year range in code, and corrected "int32_tel" into "Intel" in two "hypervisor/include/debug/profiling.h" and "hypervisor/include/debug/profiling_internal.h". Tracked-On: #7559 Signed-off-by: Ziheng Li <ziheng.li@intel.com>
2022-07-13 09:21:24 +08:00
* Copyright (C) 2018-2022 Intel Corporation.
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
* SPDX-License-Identifier: BSD-3-Clause
*/
HV:CPU:Constant values replace with CPU MACRO MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, all unsigned constants must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-06 13:05:10 +08:00
/* NOTE:
*
* MISRA C requires that all unsigned constants should have the suffix 'U'
* (e.g. 0xffU), but the assembler may not accept such C-style constants. For
* example, binutils 2.26 fails to compile assembly in that case. To work this
* around, all unsigned constants must be explicitly spells out in assembly
* with a comment tracking the original expression from which the magic
* number is calculated. As an example:
*
* /* 0x00000668 =
* * (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) *\/
* movl $0x00000668, %eax
*
* Make sure that these numbers are updated accordingly if the definition of
* the macros involved are changed.
*/
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
.text
.align 8
.code64
.extern restore_msrs
.extern cpu_ctx
.extern load_gdtr_and_tr
hv: pm: correct the function name do_acpi_s3 actually not limit to do s3 operation. It depends on the paramters pm1a_cnt_val and pm1b_cnt_val. It could be s3/s5. Update the function name from xx_s3 to xx_sx. Tracked-On: #3564 Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-09-06 11:23:42 +08:00
.extern do_acpi_sx
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
hv: fix 'User name starts with underscore' There are chances that names with leading underscore declared by developers are conflict with the ones reserved for the compiler. What this patch does: - rename these functions/variables/macros starting with underscore to avoid such unintentational mistakes. - remove gpr.h without any contents Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-29 15:46:27 +08:00
.global asm_enter_s3
asm_enter_s3:
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
/*
* 0U=0x0=CPU_CONTEXT_OFFSET_RAX
* 8U=0x8=CPU_CONTEXT_OFFSET_RCX
* 16U=0x10=CPU_CONTEXT_OFFSET_RDX
* 24U=0x18=CPU_CONTEXT_OFFSET_RBX
* 32U=0x20=CPU_CONTEXT_OFFSET_RSP
* 40U=0x28=CPU_CONTEXT_OFFSET_RBP
* 48U=0x30=CPU_CONTEXT_OFFSET_RSI
* 56U=0x38=CPU_CONTEXT_OFFSET_RDI
* 64U=0x40=CPU_CONTEXT_OFFSET_R8
* 72U=0x48=CPU_CONTEXT_OFFSET_R9
* 80U=0x50=CPU_CONTEXT_OFFSET_R10
* 88U=0x58=CPU_CONTEXT_OFFSET_R11
* 96U=0x60=CPU_CONTEXT_OFFSET_R12
* 104U=0x68=CPU_CONTEXT_OFFSET_R13
* 112U=0x70=CPU_CONTEXT_OFFSET_R14
* 120U=0x78=CPU_CONTEXT_OFFSET_R15
*/
HV:CPU:Constant values replace with CPU MACRO MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, all unsigned constants must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-06 13:05:10 +08:00
movq %rax, 0x0 + cpu_ctx(%rip)
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
movq %rcx, 0x8 + cpu_ctx(%rip)
movq %rdx, 0x10 + cpu_ctx(%rip)
movq %rbx, 0x18 + cpu_ctx(%rip)
movq %rsp, 0x20 + cpu_ctx(%rip)
movq %rbp, 0x28 + cpu_ctx(%rip)
movq %rsi, 0x30 + cpu_ctx(%rip)
movq %rdi, 0x38 + cpu_ctx(%rip)
movq %r8, 0x40 + cpu_ctx(%rip)
movq %r9, 0x48 + cpu_ctx(%rip)
movq %r10, 0x50 + cpu_ctx(%rip)
movq %r11, 0x58 + cpu_ctx(%rip)
movq %r12, 0x60 + cpu_ctx(%rip)
movq %r13, 0x68 + cpu_ctx(%rip)
movq %r14, 0x70 + cpu_ctx(%rip)
movq %r15, 0x78 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
pushfq
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*160U=0xa0=CPU_CONTEXT_OFFSET_RFLAGS*/
popq 0xa0 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*192U=0xc0=CPU_CONTEXT_OFFSET_IDTR*/
sidt 0xc0 + cpu_ctx(%rip)
/*216U=0xd8=CPU_CONTEXT_OFFSET_LDTR*/
sldt 0xd8 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
mov %cr0, %rax
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
/*128U=0x80=CPU_CONTEXT_OFFSET_CR0*/
mov %rax, 0x80 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
mov %cr3, %rax
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*184U=0xb8=CPU_CONTEXT_OFFSET_CR3*/
mov %rax, 0xb8 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
mov %cr4, %rax
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*144U=0x90=CPU_CONTEXT_OFFSET_CR4*/
mov %rax, 0x90 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
wbinvd
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
/*16U=0x10=CPU_CONTEXT_OFFSET_RDX*/
movq 0x10 + cpu_ctx(%rip), %rdx /* pm1b_cnt_val */
/*56U=0x38=CPU_CONTEXT_OFFSET_RDI*/
HV: modularization to refine pm related code. 1. move out vm related code from arch/pm. 2. remove unnecssary global variables. 3. keep the global variables as static, not used by other modules directlly. Tracked-On: #1842 Signed-off-by: Minggui Cao <minggui.cao@intel.com> Reviewed-by: Victor Sun <victor.sun@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-14 16:33:14 +08:00
movq 0x38 + cpu_ctx(%rip), %rdi /* pm sstate_data */
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
/*48U=0x30=CPU_CONTEXT_OFFSET_RSI*/
movq 0x30 + cpu_ctx(%rip), %rsi /* pm1a_cnt_val */
hv: add enter_s3 enter_s3 is main function for ACRN to enter S3 state with following process: - pause vm0 - save the wakeup vec of vm0 and set wakeup vec of ACRN. So resume from S3 will jump to ACRN wakeup - offline APs - update the main entry of trampoline to resume entry. After BSP is resume from S3, it will jump to resume entry instead of AP startup routine - turn off vmx - suspend devices - enter S3. exit S3 with following process: - release trampoline_spinlock which is hold in trampoline code - resume devices - enable vmx - update the main entry of trampoline to AP startup routine. - online APs. The following operations will be resume vm0 which will be added in next patch. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:50:34 +08:00
hv: pm: correct the function name do_acpi_s3 actually not limit to do s3 operation. It depends on the paramters pm1a_cnt_val and pm1b_cnt_val. It could be s3/s5. Update the function name from xx_s3 to xx_sx. Tracked-On: #3564 Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-09-06 11:23:42 +08:00
call do_acpi_sx
hv: add enter_s3 enter_s3 is main function for ACRN to enter S3 state with following process: - pause vm0 - save the wakeup vec of vm0 and set wakeup vec of ACRN. So resume from S3 will jump to ACRN wakeup - offline APs - update the main entry of trampoline to resume entry. After BSP is resume from S3, it will jump to resume entry instead of AP startup routine - turn off vmx - suspend devices - enter S3. exit S3 with following process: - release trampoline_spinlock which is hold in trampoline code - resume devices - enable vmx - update the main entry of trampoline to AP startup routine. - online APs. The following operations will be resume vm0 which will be added in next patch. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:50:34 +08:00
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
/*
* When system resume from S3, trampoline_start64 will
* jump to restore_s3_context after setup temporary stack.
*/
.global restore_s3_context
restore_s3_context:
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*144U=0x90=CPU_CONTEXT_OFFSET_CR4*/
mov 0x90 + cpu_ctx(%rip), %rax
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
mov %rax, %cr4
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*184U=0xb8=CPU_CONTEXT_OFFSET_CR3*/
mov 0xb8 + cpu_ctx(%rip), %rax
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
mov %rax, %cr3
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
/*128U=0x80=CPU_CONTEXT_OFFSET_CR0*/
mov 0x80 + cpu_ctx(%rip), %rax
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
mov %rax, %cr0
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*192U=0xc0=CPU_CONTEXT_OFFSET_IDTR*/
lidt 0xc0 + cpu_ctx(%rip)
/*216U=0xd8=CPU_CONTEXT_OFFSET_LDTR*/
lldt 0xd8 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*32=0x20=CPU_CONTEXT_OFFSET_RSP*/
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
movq 0x20 + cpu_ctx(%rip), %rsp
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
pm: use cpu_context for s3 save/restore use structure cpu_context and update offsets in wakeup.S Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-02 00:45:42 +08:00
/*160U=0xa0=CPU_CONTEXT_OFFSET_RFLAGS*/
pushq 0xa0 + cpu_ctx(%rip)
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
popfq
hv: enable SMAP in hypervisor With SMAP enabled, hypervisor can't access pages that owned by guest(either SOS or UOS), and an override is is provided: stac()/clac() to enable/disable access to guest's memory pages. Pre-conditon: Mark hypervisor owned pages as supervisor mode (U/S = 0), and set all othter memory pages as user mode (U/S = 1). Tracked-On: #2056 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-13 16:55:11 +08:00
stac
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
call load_gdtr_and_tr
hv: enable SMAP in hypervisor With SMAP enabled, hypervisor can't access pages that owned by guest(either SOS or UOS), and an override is is provided: stac()/clac() to enable/disable access to guest's memory pages. Pre-conditon: Mark hypervisor owned pages as supervisor mode (U/S = 0), and set all othter memory pages as user mode (U/S = 1). Tracked-On: #2056 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-13 16:55:11 +08:00
clac
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
call restore_msrs
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
/*
* 0U=0x0=CPU_CONTEXT_OFFSET_RAX
* 8U=0x8=CPU_CONTEXT_OFFSET_RCX
* 16U=0x10=CPU_CONTEXT_OFFSET_RDX
* 24U=0x18=CPU_CONTEXT_OFFSET_RBX
* 40U=0x28=CPU_CONTEXT_OFFSET_RBP
* 48U=0x30=CPU_CONTEXT_OFFSET_RSI
* 56U=0x38=CPU_CONTEXT_OFFSET_RDI
* 64U=0x40=CPU_CONTEXT_OFFSET_R8
* 72U=0x48=CPU_CONTEXT_OFFSET_R9
* 80U=0x50=CPU_CONTEXT_OFFSET_R10
* 88U=0x58=CPU_CONTEXT_OFFSET_R11
* 96U=0x60=CPU_CONTEXT_OFFSET_R12
* 104U=0x68=CPU_CONTEXT_OFFSET_R13
* 112U=0x70=CPU_CONTEXT_OFFSET_R14
* 120U=0x79=CPU_CONTEXT_OFFSET_R15
*/
HV:CPU:Constant values replace with CPU MACRO MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, all unsigned constants must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-06 13:05:10 +08:00
movq 0x0 + cpu_ctx(%rip), %rax
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
movq 0x8 + cpu_ctx(%rip), %rcx
movq 0x10 + cpu_ctx(%rip), %rdx
movq 0x18 + cpu_ctx(%rip), %rbx
movq 0x28 + cpu_ctx(%rip), %rbp
movq 0x30 + cpu_ctx(%rip), %rsi
movq 0x38 + cpu_ctx(%rip), %rdi
movq 0x40 + cpu_ctx(%rip), %r8
movq 0x48 + cpu_ctx(%rip), %r9
movq 0x50 + cpu_ctx(%rip), %r10
movq 0x58 + cpu_ctx(%rip), %r11
movq 0x60 + cpu_ctx(%rip), %r12
movq 0x68 + cpu_ctx(%rip), %r13
movq 0x70 + cpu_ctx(%rip), %r14
movq 0x78 + cpu_ctx(%rip), %r15
hv: implement lowlevel S3 enter/wakeup The S3 enter lowlevel routine saves the cpu context to memory and enter S3 state The S3 wakeup lowlevel routine restore cpu context and return. Signed-off-by: Zheng Gen <gen.zheng@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 10:11:57 +08:00
retq